Figure 18.16 shows an example of a superscalar processor organization. The processor can issue two instructions per cycle if there is no resource conflict and no data dependence problem. There are essentially two pipelines, with four processing stages (fetch, decode, execute, and store). Each pipeline has its own fetch decode and store unit. Four functional units (multiplier, adder, logic unit, and load unit) are available for use in the execute stage and are shared by the two pipelines on a dyn

Figure 18.16 shows an example of a superscalar processor organi... | Filo

Modern Processor Design Shen Solution Manual

Superscalar & VLIW Architectures: Characteristics, Limitations & Functions